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PLL Oscillator

Quartz
Phase
comparator
Low
pass
Voltage
Controlled
Oscillator
Pre-
divider
Digitally
controlled
countdown
RF-out

Figure 1: Basic block diagram of PLL oscillator

Quartz
Phase
comparator
Low
pass
Voltage
Controlled
Oscillator
Pre-
divider
Digitally
controlled
countdown
RF-out

Figure 1: Basic block diagram of PLL oscillator

Quartz
Phase
comparator
Low
pass
Voltage-
Controlled
Oscillator
Pre-
divider
Digitally
controlled
countdown
RF-out

Figure 1: Basic block diagram of PLL oscillator

PLL Oscillator

PLL Oscillator is a circuit for generating high-frequency oscillations using a phase-locked loop.

In the basic configuration, a phase-locked loop compares the phase of a crystal-stabilized reference signal with the phase of a feedback signal divided down from the output frequency into the frequency range of the reference signal. This phase comparison is used to generate the tuning voltage for the voltage-controlled oscillator (VCO).

The adjustable frequency range (or bandwidth of the phase control loop) is an important parameter for the transient response and the phase noise. The larger this bandwidth is, the faster the PLL oscillator can settle. But the narrower this control range is, the purer the output signal is. As a compromise, a bandwidth of 15% is usually chosen.

Crystal oscillator

The crystal oscillator usually oscillates on a standard frequency in the range between 10 and 100 MHz. If several PLL oscillators are used (as is common with active phased array antennas), then a central, highly accurate crystal oscillator is used, which can even be synchronized with a GPS time standard.

Reference
f(to test)
charge
currents

Figure 2: Phase comparator wiring

Reference
f(to test)
charge
currents

Figure 2: Phase comparator wiring

Reference
f(to test)
charge
currents

Figure 2: Phase comparator wiring

Phase comparator

The phase comparator consists of two D-flipflops and several NAND gates. The positive edges of the frequencies applied to the input set the respective flipflop, and the H potential hardwired to the data input appears at the Q output. When both flip-flops are set, the gate switches the reset input low and both flip-flops wait for the next positive edge. If there is a phase difference, pulses are generated for the time of the phase differences. If the frequency is too high, then the lower flipflop switches earlier than the upper one, a longer pulse appears on the lower output line before both flipflops are set to zero. If the frequency is too low, then the pulse on the upper line is longer than the small spike on the lower line. External circuitry with field effect transistors converts these pulses into charge or discharge currents for a capacitor. A positive current (upper flipflop) increases and a negative current (lower flipflop)decreases the tuning voltage.

Lowpass

Capacitors included in the low-pass filter smooth the tuning voltage and reduce the influence of the pulse-like current peaks.

Counter circuits

Counter circuits allow the VCO to oscillate at a higher frequency than the reference frequency. For binary counters, this can only be at a multiple of the reference frequency. Therefore, this reference frequency should be at most equal to the channel spacing when the PLL oscillator is used for communication purposes.